In a system wherein there are multiple devices that share a common main memory, and each device can individually cache data from addresses in main memory, to ensure data consistency among devices, a mechanism often used is known as hardware enforced cache coherency of data. A portion of this mechanism is known as “snooping”. When a processor, or other snooping master, makes a coherent access to main memory, that access is first broadcast to all the other snooping masters (the “non-originating snooping masters”) as a “snoop request” by a central resource, called the “Bus Macro”. The non-originating snooping masters react to the snoop request by returning a snoop result that indicates the state of that master's cache for the address provided with the snoop request. The bus macro receives all the snoop results and takes one of several possible actions based on the values of the snoop results. One action may be to allow the main memory access to complete. Another action may be to delay the main memory access until the non-originating snooping masters write modified data from their caches back to main memory. Other actions are also possible. Note that the most common type of snooping master with a cache is a processor, although other devices, such as DMA controllers, can be used.
Typically, when memory coherence is required, all snooping masters continuously snoop all main memory accesses to ensure data consistency. However, there are often times when a non-originating master knows that it cannot contain the data for a particular snoop request. In these cases, it is desirable for the non-originating master to not snoop its resources. This is desirable for several reasons:
1) Unnecessary power is consumed by the non-originating snooping masters that cannot contain the requested data checking their resources.
2) Once the request is made to the non-originating snooping master, that snooping master must snoop its cache to see if it has a cached copy of the requested address location. This snooping of the cache may interfere with the non-originating snooping master from accessing the cache locally, thus decreasing the performance of the non-originating snooping master.
3) If one of the non-originating snooping masters takes many clock cycles to snoop its cache the originating master will be stalled until the slowest non-originating snooping master has completed the snoop, thus decreasing the originating master's performance.